Tuesday 14th November 2017

Exascale Applications and Software Conference (EASC18) - Conference Update

Conference update: Andreas Olofsson (program Manager in the Microsystems Technology Office at DARPA) and Satoshi Matsuoka (Professor of Global Scientific Information Center and Tokyo Institute of Technology) have confirmed as two of our keynote speakers.

Before working at DARPA, Andreas Olofsson founded Adapteva and created the Epiphany many-core processor. A number of variants of this chip, with 16, 64 and 1024 cores have been designed which are all very energy efficient, cheap and powerful which makes them very interesting for use in HPC and embedded systems alike. Adapteva also produced the Parallella, a single board computer for less than $99, which combines an Epiphany chip with standard CPU. Andreas is therefore at the cutting edge of chip design technology and a strong advocate of the fact that you don't necessarily need the money and resources of extremely large chip companies to make innovative hardware.

Satoshi Matsuoka is a Full Professor at the Global Scientific Information and Computing Center (GSIC). He is the leader of the TSUBAME series of supercomputers, including TSUBAME2.0 which was the first supercomputer in Japan to exceed Petaflop performance and TSUBAME 3.0 which was number 1 in the world for power efficiency in the Green 500 2017 list. Satoshi has a wealth of experience and knowledge in HPC and is one of the key global players pushing forward exascale technologies.

Call for participation

You are warmly invited to participate in the 5th Exascale Applications and Software Conference (EASC 2018), to be held in Edinburgh, UK on the 17-19 April 2018. We are seeking novel contributions in all areas associated with applications, tools, software programming models and libraries, and other technologies necessary to exploit future exascale systems.

Submissions are in the form of a one page abstract for oral or poster presentation and the deadline is the 4th of December 2017. More details, along with participation guidelines can be found on the EASC2018 homepage.

More information

For full information please see the EASC2018 homepage.

HPC-Europa: EC-funded research visits using High Performance Computing

HPC-Europa is an EC-funded programme which allows researchers to carry out short "transnational access" visits to collaborate with a research department working in a similar field while at the same time providing access to High Performance Computing facilities.

We would like to remind people that the second call for HPC Europa applicants closes Thursday 16th November 2017 (23:59 CET).

Future closing dates will be held approximately every 3 months, and the HPC-Europa3 programme continues until April 2021.

If you have not heard of HPC-Europa before, further information and the on-line application form can be found at and any questions not answered by the information on the webpage can be emailed to

Performance portability on current and upcoming archictures: Virtual Tutorial POSTPONED - new date tba

Apologies: This tutorial has now been postponed and a new date will be announced as soon as it is confirmed.

Further details, including joining instructions, can be found at: Virtual Tutorials and Webinars

Upcoming Training Opportunities

  • GPU Programming with CUDA 21-22 November 2017 Daresbury *Registration closes 5pm 14th November*
  • Hands-on Introduction to HPC 4-5 December 2017 Alan Turing Institute London
  • Software Carpentry 11-12 December 2017 Imperial College London
  • Advanced OpenMP (in conjuction with INTERTWinE) 12-14 December 2017 Imperial College London
Full details and registration...