Xeon Phi

The Xeon Phi is Intel's recently released accelerator, which is attracting a lot of interest as it has a familiar x86 CPU architecture as opposed to the radically different architectures of GPUs. This course will cover the Xeon Phi architecture and how to use the Intel compiler and associated tools to exploit its full computational potential using a variety of offload models. It will also cover issues relating to using the Xeon Phi as part of a larger HPC system.

If you are familiar with multicore architectures then you are welcome to register for this course on its own. If not, you should consider attending the 2-day "Multicore Programming" course which immediately precedes.

This course is being run collaboratively between the ARCHER and DiRAC HPC services, and with the Intel Parallel Computing Centres at EPCC and Cambridge.

This course is free to all academics.

Intended learning outcomes

On completion of this course students should be able to:

  • Describe the Xeon Phi architecture.
  • Use the Intel compiler and associated tools to exploit its full computational potential.
  • Use a variety of offload models to accelerate code.
  • Understand how the Xeon Phi operates as part of a larger HPC system.

Pre-requisites

Programming Languages:

  • Ability to program in C, C++ or Fortran.

Timetable

Day 1

  • 09.30 - 10.00: Introduction to the Xeon Phi
  • 10.00 - 10.45: Programming models for the Xeon Phi
  • 10.45 - 11.00: Practical: Introduction to Xeon Phi
  • 11.00 - 11.30: Break
  • 11.30 - 12:00: Achievable performance on Xeon Phi
  • 12.00 - 12.30: Native model programming
  • 12.30 - 13.00: Practical: Native mode
  • 13.00 - 14.00: Lunch
  • 14.00 - 15.00: Off-loading to the Xeon Phi
  • 15.00 - 15.30: Practical: Off-loading
  • 15.30 - 16.00: Break
  • 16.00 - 16.30: Case studies: Porting to the Xeon Phi
  • 16.30 - 17.30: Practical: Continue the practicals

Day 2

  • 09.30 - 09.45: Recap of Xeon Phi
  • 09.45 - 10.30: Vectorisation
  • 10.30 - 11.00: Practical: Vectorisation
  • 11.00 - 11.30: Break
  • 11.30 - 12.00: Practical: Vectorisation
  • 12:00 - 13.00: Serial Optimisation
  • 13.00 - 14.00: Lunch
  • 14.00 - 15.00: Practical: Serial optimisation
  • 15.00 - 15.30: Optimising MPI and off-loading
  • 15.30 - 16.00: Break
  • 16.00 - 17.00: Practical: Continue practicals or port own code
  • 17.00 - 17.30: Summary and finish

Course Materials

Slides and exercise material for this course will be available soon.

Location

The course will be held in EPCC, Edinburgh.

Registration

Please use the registration page to register for ARCHER courses.

Questions?

If you have any questions please contact the ARCHER Helpdesk.